Dynamically Reconfigurable HW
نویسندگان
چکیده
The paper addresses the problem of mapping an application speciied as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconngurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to diierent temporal segments and scheduling task execution, reconnguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The eeectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.
منابع مشابه
HW/SW codesign techniques for dynamically reconfigurable architectures
Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. However, no previous work has been carried out in order to define a HW/SW codesign methodology with dynamic scheduling for run-time reconfigurable architectures. In addition, all previous approaches to reconfigurable computing multicontext scheduling are based on static-sch...
متن کاملA Unified HW/SW Operating System for Partially Runtime Reconfigurable FPGA
Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. We present an OS for hybrid computing systems consisting of both CPUs and PRTR FPGAs. The OS is based on Linux, and provides unified interfaces for both HW and SW processes to ease the design of such hybrid systems. The scheduler of HW processes is implemented on the hardware, to ...
متن کاملEfficient 2D Area Management and Online Task Placement on Runtime Reconfigurable FPGAs
Partial runtime reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadl...
متن کاملDynamically Co-synthesis of H/w & S/w and Optimization in Reconfigurable Embedded System
Field Programming Gate Array (FPGA) play an important role in reconfigurable computing. Reconfigurable computing has been used to build reconfigurable embedded system. Reconfigurable embedded System is dynamically changing in the hardware circuit at runtime with the reconfigurable characteristic of Programmable Logic Devices like FPGA, to give the system advantages in both hardware and software...
متن کاملImplantation of Dynamically Reconfigurable Systems on Chip with OS Support
This work presents the implementation of dynamically reconfigurable system with operating system support specifically Linux. The presented work combines both HW and SW flows where the complex parts of the architecture are designed to HW modules. These HW modules can be reconfigured on the fly by using partial dynamic reconfiguration. In our work, we are using floating point computation unit as ...
متن کاملEfficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs
Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadl...
متن کامل